Reference:
Holger Giese and Sven Burmester, "Analysis and Synthesis for Parameterized Timed Sequence Diagrams", in Holger Giese, Ingolf Krüger, Eds., Proc. of the 3rd International Workshop on Scenarios and State Machines: Models, Algorithms, and Tools (ICSE 2003 Workshop W5S), Edinburgh, Scotland, pp. 43-50, IEEE, May 2004.
Abstract:
Today, an increasing demand for high quality real-time software for complex, safety-critical systems results from the fact that more ambitious and complex technical systems are built. In the development of such systems, a crucial step is the design and formal verification of the real-time interaction of the components to ensure the correctness and safe operation of the overall system. We propose to ease this cumbersome design step by supporting the analysis of conflicts between timed scenarios and the scenario-based synthesis of the required component behavior. Such a synthesis procedure, which requires as its input a set of timed scenarios, results in a set of Statecharts that realize the given scenarios. By supporting even parameterized timed scenarios, the approach permits to avoid too early decisions on specific values for the time constraints while still being able to check them. The paper describes the application of the approach and the available prototypical tool support by means of a running example.
Links:
@InProceedings{Giese&Burmester2004,
AUTHOR = {Giese, Holger and Burmester, Sven},
TITLE = {{Analysis and Synthesis for Parameterized Timed Sequence Diagrams}},
YEAR = {2004},
MONTH = {May},
BOOKTITLE = {Proc. of the 3rd International Workshop on Scenarios and State Machines: Models, Algorithms, and Tools (ICSE 2003 Workshop W5S), Edinburgh, Scotland},
PAGES = {43-50},
EDITOR = {Giese, Holger and Kr\"{u}ger, Ingolf},
PUBLISHER = {IEEE},
PDF = {uploads/pdf/scesm.pdf},
ABSTRACT = {Today, an increasing demand for high quality real-time software for complex, safety-critical systems results from the fact that more ambitious and complex technical systems are built. In the development of such systems, a crucial step is the design and formal verification of the real-time interaction of the components to ensure the correctness and safe operation of the overall system. We propose to ease this cumbersome design step by supporting the analysis of conflicts between timed scenarios and the scenario-based synthesis of the required component behavior. Such a synthesis procedure, which requires as its input a set of timed scenarios, results in a set of Statecharts that realize the given scenarios. By supporting even parameterized timed scenarios, the approach permits to avoid too early decisions on specific values for the time constraints while still being able to check them. The paper describes the application of the approach and the available prototypical tool support by means of a running example.}
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