Prof. Dr. Tilmann Rabl


CXL Buffer Management Paper Accepted at HardBD & Active '24

Our paper A Three-Tier Buffer Manager Integrating CXL Device Memory for Database Systems, by Niklas Riekenbrauck, Marcel Weisgut, Daniel Lindner, Tilmann Rabl was accepted at HardBD & Active '24 (co-located with ICDE '24).


Compute Express Link (CXL) is a new interconnect for attaching byte-addressable memory on PCI-connected devices to a CPU. The interconnect allows a database system to place data on local memory, CXL device memory, and persistent disk storage. While three-tier buffer managers integrating persistent memory (PMem) exist, CXL device memory has not been integrated into a multi-tier buffer manager architecture. Existing three-tier buffer managers integrating PMem use pointer swizzling to address buffered pages, which is an invasive and hard-to-implement technique. This work presents a three-tier buffer manager that integrates CXL device memory. The design combines hardware-supported virtual memory for efficient page translation and a probabilistic page migration policy to determine on which tier pages are located. We demonstrate that these approaches combined allow a simple integration of CXL device memory into a database system. We evaluate the buffer manager with different configurations and workloads based on the YCSB benchmark on a CXL Type 3 device prototype. Our evaluation demonstrates that expanding a server’s memory with CXL device memory can be used to keep more data in memory and to reduce spilling data to slow disk storage.