Instructors
Prof. Dr. Tilmann Rabl, Martin Boissier, Marcel Weisgut, Florian Schmeller
Description
Hardware development continuously advances, with different technologies improving at different paces. While the number of transistors in a CPU package grows, the single-core performance stagnates due to physical limitations. These trends require changes in data processing to keep database management systems efficient. In this lecture, we will take a look at current computer architectures and accelerator technologies and how they can be used for efficient data processing. We will cover CPU and memory architecture, the storage hierarchy, modern memory and storage technologies, such as NVMe, fast interconnects, such as Infiniband, NVLink, and CXL, and accelerators, such as GPUs and FPGAs. The course has a significant practical part, where the students learn to implement data structures and algorithms tailored to hardware-conscious data processing.
Literature
- Structured Computer Organization, Andrew S. Tanenbaum, Todd Austin, 2012, 978-0132916523
- A Course in In-Memory Data Management: The Inner Mechanics of In-Memory Databases, Hasso Plattner, 2014, 978-3642552694
Announcements
- Course management will be done using the HPI Moodle
- The lectures will be held on-site at HPI (L-E.03)
- Non-HPI participants: please send us an email to get access to the Moodle
- All lectures are recorded and available on TeleTask
Topics
The lectures will be held on Tuesdays (L.E-03) and Wednesdays (L.E-03) at 11:00 o'clock.
| Date | Tuesday | Date | Wednesday |
|---|
| 8.4. | Intro to HDP - moved to HS 3 | 9.4. | DB Basics - Online |
| 15.4. | Performance Management | 16.4. | CPU Basics |
| 22.4. | CPU Basics | 23.4. | CPU Instructions |
| 29.4. | Prefetching | 30.4. | Execution Models - moved to HS 1 |
| 6.5. | Task I (Query Processing) | 7.5. | SIMD I |
| 13.5. | SIMD I | 14.5. | Data Structures |
| 20.5. | Profiling Session | 21.5. | Multicore I - moved to L-1.06 |
| 27.5. | Task II (SIMD) | 28.5. | Multicore II |
| 3.6. | Locking | 4.6. | NUMA |
| 10.6. | Storage | 11.6. | Compute Express Link |
| 17.6. | Task III (Buffer Manager) | 18.6. | Networking |
| 24.6. | SIGMOD Week | 25.6. | SIGMOD Week |
| 1.7. | GPU I - moved to L-1.06 | 2.7. | GPU II |
| 8.7. | RDMA | 9.7. | FPGA I |
| 15.7. | Task IV (GPU Join) | 16.7. | Data Center Tour - Entry Build. L 11:15 am |
Grading
The programming tasks determine 100% of the grade, there is no final exam. In addition to the graded tasks, each student will present their solution for one task in a short individual meeting with the teaching team. We will randomly select students for each current task throughout the semester. Passing this discussion is mandatory to complete the course. The programming tasks will be 25% each.
Prerequisites
This course is aimed towards students with knowledge in database and/or big data systems. Ideally, students have attended at least one of Big Data Systems, Distributed Data Management, Database Systems II, or similar. The programming tasks are all in C++, so students should be comfortable with it. We provide a small example task (see Example Coding Task in Moodle) that students can do before the course to see whether they are comfortable with C++. If you are not able to solve this task, you will probably have a very hard time in the course, as this is the very minimum level needed to complete the other tasks.
